Method for programmable integrated passive devices

ABSTRACT

A method for endowing an integrated passive device array structure with a programmable value during manufacturing. The method includes forming a substantially conductive first layer and forming a plurality of passive device array elements of the integrated passive device array structure above the substantially conductive first layer. The method further includes forming an insulating layer above the plurality of passive device array elements. There is further included selectively forming vais the insulating layer. The vias facilitate electrical connections between selected ones of the plurality of passive device array elements with a substantially conductive second layer subsequently deposited above the insulating layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application claims priority from U.S. Provisional PatentApplication No. 60/028,778 filed Oct. 18, 1996.

BACKGROUND OF THE INVENTION

The present invention relates to the manufacture of integrated circuits(IC's). More particularly, the present invention relates to programmablecapacitors, and methods therefor, that render the value of the capacitorselectable during manufacturing.

Integrated circuits integrate many discrete functions and componentsinto one “integrated” circuit. One of the reasons integrated circuitspresently predominate over discrete component solutions is because ofthe costs involved in manufacturing, assembling, and testing discretebased circuits. For example, present day microprocessors incorporatemore than one million transistors into a square package less than 5 cmon each side. The same number of transistors, discretely and separatelyplaced on a printed circuit board, would require several orders ofmagnitude more space. Other advantages of integrated circuit technology,which are well known to those skilled in the art, include reliabilityand cost.

The miniaturization that present day integrated circuit technology, andthe benefits that such technology bestows, are applicable to passivecomponent integration as well. When passive devices, e.g., capacitors,resistors, inductors, and the like, are integrated, they are referred toherein as passive component integrated circuits.

In the design of passive thin film integrated circuits, for example,capacitors of different values are needed. By way of example, in thedesign of a family of filters or terminators, resistors and capacitorsare combined in different configurations and values to provide differentfunctionality and performance. In prior art, this is typicallyaccomplished by a custom design and integrated circuit layoutconfiguration for each type of circuit and for each value. This processis time consuming, more prone to errors and less economical.

In the description that follows, an integrated capacitor is selected fordiscussion. It should be borne in mine, however, that the inventiveconcepts herein also apply to other types of passive devices, e.g.,resistors, inductors, and the like. In the prior art, when anapplication requires an integrated capacitor having a value that ispreviously unavailable, a new custom design is necessitated to create anintegrated circuit having a capacitor with the desired value. Thiscustom design approach requires a substantial amount of time, effort,and expense since a custom design with specific capacitance values andcharacteristics must be laid out and verified, the required masks mustbe created, and manufacturing steps must be tailored to fabricate therequired integrated circuits. As can be appreciated from the foregoing,the custom design approach is disadvantageous in view of the greatvariety of device values required by modern electronic equipment.

In view of the foregoing, what is desired are passive componentintegrated circuit structures and methods therefor, which can implementa wide range of values in a given single design. This alleviates all theabove mentioned limitations of prior art custom design approaches,thereby providing quicker design turnaround time, fewer design errorsand a lower manufacturing cost.

SUMMARY OF THE INVENTION

The present invention relates, in one embodiment, to a method forendowing an integrated passive device array structure with aprogrammable value during manufacturing. The method includes forming asubstantially conductive first layer and forming a plurality of passivedevice array elements of the integrated passive device array structureabove the substantially conductive first layer. The method furtherincludes forming an insulating layer above the plurality of passivedevice array elements. There is further included selectively formingvias in the insulating layer. The vias facilitate electrical connectionsbetween selected ones of the plurality of passive device array elementswith a substantially conductive second layer subsequently depositedabove the insulating layer.

In another embodiment, the invention relates to a method for forming anintegrated passive device array structure having a programmable value.The method includes forming a substantially conductive first layer, andelectrically coupling the substantially conductive first layer with aplurality of passive device array elements of the integrated passivedevice array structure. The plurality of passive device array elementsis disposed above the substantially conductive first layer. There isalso included electrically coupling selected ones of the plurality ofpassive device array elements with a substantially conductive secondlayer to form the integrated passive device array structure. Theselected ones of the plurality of passive device array elementsrepresent a subset of the plurality of passive device array elements.

In yet another embodiment, the invention relates to an integratedprogrammable passive device array structure, which includes a firstnode, and a plurality of passive device array elements electricallycoupled to the first node. The integrated programmable passive devicearray structure further includes a second node electrically coupled, ina selective manner, to selected ones of the plurality of passive devicearray elements. The selected one of the plurality of passive devicearray elements represent a subset of the plurality of passive devicearray elements, wherein a value of the programmable passive device arraystructure is substantially determined by an aggregate of values of theselected ones of the plurality of passive device array elements.

In another embodiment, the invention relates to a capacitor arraystructure having multiple capacitor array elements. During production,the individual capacitor array elements are selected for inclusion intoor exclusion out of the final capacitor structure. An included capacitorarray element contributes its capacitance value to the capacitance valueof the final capacitor structure. In contrast, the capacitance value ofan excluded capacitor array element makes no contribution to thecapacitance value of the final capacitor structure.

In another embodiment, the capacitor array elements are binary related,in accordance with this embodiment, a given array element has twice thecapacitance value of its smaller counterpart. For example, the cellsurface area of a successive capacitor array element increases by afactor of 2 relative to its immediately smaller counterpart. Becausecapacitance is proportional to the surface area of the plates formingthe capacitor, by providing n distinct cells in the array structure, 2ndifferent capacitance values may be available for each such arraystructure.

In accordance with yet another embodiment of the present invention, agiven capacitor array element is selected for inclusion by providing itwith a contact, thereby permitting an electrical path to exist betweenits plates and the nodes of the final capacitor structure through theprovided contact. On the other hand, another given capacitor arrayelement is excluded from the final capacitor structure when no contactis provided for it, thereby inhibiting the formation of an electricalpath between its plates and the nodes of the final capacitor structure.In this manner, individual capacitor array elements of a capacitor arraystructure may be programmably selected for inclusion or exclusion byappropriately designing the contact mask.

These and other advantages of the present invention will become apparentupon reading the following detailed descriptions and studying thevarious figures of the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a) and 1(b) are a schematics illustrating, in accordance withone aspect of the present invention, capacitor array structures havingcapacitors coupled in parallel for implementing the programmablecapacitors of the present invention.

FIG. 1(c) is a symbolic circuit diagram illustrating the contributionmade by selected and non-selected capacitor array members to thecapacitance value of the final capacitor structure.

FIG. 2 shows, in accordance with one embodiment of the presentinvention, a top plane view of a capacitor array layout.

FIGS. 3a-3j illustrate, in accordance with one embodiment of the presentinvention, the relevant steps involved in the fabrication andprogramming of a capacitor array structure.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In accordance with one aspect of the present invention, the value of theinventive programmable capacitor may be rendered selectable duringmanufacturing by fabricating the capacitor as a programmable capacitorarray structure. The value of the capacitor that results may beprogrammably determined during manufacturing by the selective inclusionof individual capacitor array members. Capacitor array members which areincorporated into the final programmable capacitor array structurecontribute to the capacitance value of the resulting capacitor. On theother hand, capacitor array members which are not incorporated into thefinal programmable array structure do not contribute to the capacitancevalue of that resulting capacitor. The above concept may be betterunderstood with reference to the Figures below.

FIGS. 1(a) through 1(c) illustrate the concept that underlies theprogrammable capacitor array in accordance with one aspect of thepresent invention. FIG. 1a illustrates a programmable capacitor C, whichcomprises a plurality of programmably related capacitor array members,C₁, C₂, C₃ . . . C_(n). The programmably related capacitor array membersC₁, . . . C_(n), are arranges such that each, if selected, may becoupled in parallel with others in the programmable capacitor array. Asis readily recognizable by those skilled in the art, the effectivecapacitance value of the programmable capacitor array of FIG. 1a equalsthe cummulative capacitance value of the capacitor array members thatare coupled to nodes 100 and 102 in paralleL In other words, the valueof programmable capacitor C between nodes 100 and 102 is determined bywhich of capacitor array members C₁. . . C_(n) are incorporated into thefinal capacitor structure.

In one embodiment, the capacitor array members C₁ through C_(n) arerelated to one another in a binary manner. In other words, the values ofthe capacitor array members are successively increased by a factor of 2.In FIG. 1b, for example, there are shown a programmable capacitor arraycomprising six capacitor array members C₁ . . . C₆. When the capacitorarray members C₁ . . . C₆ are binary related, capacitor array member C₂has twice the capacitance value of capacitor array member C₁; capacitorarray member C₃ has twice the capacitance value of capacitor arraymember C₂; and so on. It should be recognized that the capacitance valueof a capacitor array member C_(m) equals 2^((m−1)) times the capacitancevalue of the smallest capacitor array member C₁ (m being an arbitraryinteger between 1 and n, the total number of capacitor array members inthe programmable capacitor array).

It should be noted that although binary related capacitor array membersare discussed herein to facilitate ease of understanding, thecapacitance values of the capacitor array members may be related to oneanother via any predetermined relationship. For example, the capacitancevalues among the capacitor array members may be related in accordance toa linear, geometric, logarithmic, or exponential relationship. Ofcourse, they may also relate to one another in any other arbitrary,predefined manner.

In FIG. 1b, capacitor array members C₂ and C₃ are not incorporated intothe final capacitor structure. As such, the capacitancevalue ofthecapacitor structure of FIG. 1b substantially equals to the sum of thecapacitance values of capacitor array members C₁, C₄, C₅, and C₆(orC₁+8C₁+16C₁+32C₁=57C₁). Other capacitance values may be obtained, as canbe appreciated from the foregoing, by selectively incorporating orremoving the individual capacitor array members from the final capacitorstructure.

Depending on the particular fabrication technology employed, the layoutof the integrated circuit may, in some cases, give rise to parasiticcapacitance between the layers in some structures. The parasiticcapacitance associated with a given capacitor array member maycontribute to the capacitance value of the final capacitor structureeven if that particular capacitor array member is not incorporated intothe final capacitor structure. To illustrate this concept, FIG. 1csymbolically illustrates the contribution of each included and excludedcapacitor array member to the capacitance value of the final capacitorstructure of FIG. 1b.

Referring to FIG. 1c, capacitor array member C1 is selected forincorporation. Accordingly, its capacitance value contributes to theresultant capacitance value of the final capacitor structure of FIG. 1b.In the context of FIG. 1c the incorporation of capacitor array member C1is illustrated symbolically by the connection of capacitor C1 to nodes100 and 102.

Capacitor array member C₂ is not selected for incorporation.Accordingly, its capacitance value does not contribute to the resultantcapacitance value of the final capacitor structure of FIG. 1b. As shownin FIG. 1c, however, the parasitic capacitance value associated withcapacitor array member C₂ still contributes to the capacitance value ofthe final capacitor structure. As a result, a parasitic capacitor C_(2p)(where p denotes parasitic capacitance) is symbolically coupled to node100 in FIG. 1c. Likewise, capacitor array member C₃ is not selected. Asshown in FIG. 1c, the parasitic capacitor C_(3p), which is associatedwith capacitor array member C₃, still makes its contribution to thecapacitance value of the resultant capacitor structure.

Finally, capacitor array members C₄ and C₅ are selected forincorporation. As a result, their capacitance values contribute to thevalue of the capacitor structure that results, as shown in FIG. 1c. FIG.1c is also useful for visualizing the programmable aspect of theinventive capacitor array structure. When a given capacitor array memberis selected for incorporation into the final capacitor structure, itscapacitor may be thought of as being coupled to a capacitor node (node100 in the case of FIG. 1c) by a switch. When a given capacitor arraymember is not selected for incorporation into the final capacitorstructure, its capacitor is not coupled to the capacitor nodes. Instead,the parasitic capacitor associated with the non-selected capacitor arraymember may then be thought of as being coupled to the capacitor nodes.

FIG. 2 illustrates, in accordance with one embodiment of the presentinvention, the layout of a programmable capacitor array. For ease ofdiscussion, the capacitor array members of FIG. 2 are binary relatedalthough, as noted earlier, other relationships may well be employed.

As is well known, a capacitor is created by placing a dielectric mediumof a certain thickness between two conductive regions, or plates, withthe capacitance being directly proportional to the surface area of theplates in contact with the dielectric; directly proportional to thedielectric constant and inversely proportional to the dielectricthickness. In this manner, for a given dielectric constant andthickness, if the surface area is doubled, the capacitance is alsodoubled. In FIG. 2, the surface area of capacitor C₂ is twice that ofcapacitor C₁. Similarly, the capacitance of capacitor C₃ is twice thatof capacitor C₂, and that of C₄ is twice that of capacitor C₃, and soon.

In accordance with one aspect of the present invention, every capacitorarray member of a programmable capacitor array is fabricated, completewith its plates and dielectric layer irrespective of whether thatcapacitor array member is incorporated into the final capacitorstructure. To select a capacitor array member for incorporation, acontact is created with a capacitor plate (typically but not necessarilythe upper plate) to facilitate the formation of a conduction pathbetween a common conductor and that capacitor plate. The commonconductor represents a node of the final capacitor structure, e.g., node100 of FIGS. 1a, 1b, and 1c. Consequently, the provision of a contactpermits the selected capacitor array member to be coupled to the commonconductor, and to the remainder of the resultant capacitor structure, ina parallel fashion with other selected capacitor array members.

If a capacitor array member is not selected for incorporation into thefinal capacitor array structure, no contact is provided for thatcapacitor array member. Consequently, there is no conduction pathbetween the plate of that non-selected capacitor and the commonconductor, and the capacitor array member is essentially “decoupled,”electrically speaking, from the remainder of the resultant capacitorstructure.

The above concept may be better understood with reference to FIGS. 3a-3jbelow. FIGS. 3a-3j illustrate, in accordance with one embodiment of thepresent invention, a manufacturing method whereby a programmablecapacitor array is created and selected ones of the array's members areprogrammably incorporated into the final capacitor structure. FIG. 3ashows the process starting with an n+type substrate 30. FIG. 3b shows ap−type⁻epitaxial layer 32, which is grown on n+type substrate 30 using aconventional semiconductor manufacturing technique.

In FIG. 3c, a deep n⁺diffusion through a selected portion of p−typeepitaxial layer 32, through to substrate 30, is performed usingconventional masking and diffusion techniques. This n⁺region 34 servesas the bottom plate of the capacitor array members to be subsequentlyformed. The region to be diffused is selected so that it lies underneaththe entirety of the capacitor array. In addition, the n⁺region serves asa low resistance path to the bottom of the wafer where physical contactis eventually made to the bottom capacitor plate and to insure that thecapacitor structure that results does not vary with applied voltage (inthe manner expected of a standard MOS gate transistor).

Referring to FIG. 1(c), for example, the bottom plate of capacitors C₁,through C₆ are electrically connected. For this reason and as will beshown herein, the selective incorporation of the capacitor array membersis performed using the top plates of the capacitor array members.

In FIG. 3d, field oxidation is selectively performed to separate theindividual capacitor array member from one another. This field oxidationis performed using conventional masking and deposition techniques. Asshown next in FIG. 3e, a selective gate oxidation is performed. Gateoxide regions 38a and 38b are grown on the portions of the n⁺region 34that are not covered by the field oxide regions 36. These gate oxideregions 38(a) and 38(b) form the dielectric of the capacitor arrayelements of the programmable capacitor array. In the preferredembodiment, the dielectric is silicon dioxide ( SiO₂). However, thedielectric may represent a layer of silicon nitride, a silicondioxide/silicon nitsride sandwich combination, or any other dielectricmaterial.

Next, a polysilicon layer is deposited and masked, as shown in FIG. 3fThese polysilicon regions 40a and 40b form the top plates of thecapacitor array elements associated with dielectric regions 38a and 38b.

Next, an intermediate oxide layer 42 is then applied as shown in FIG.3g. This intermediate oxide layer 42 electrically separates theindividual capacitor array elements from a subsequently depositedconductive layer.

In FIG. 3g, the capacitor array is essentially “unprogrammed.” At thisstage, the wafer prepared in accordance with this invention may bestored until a customer's specification for a product is received. Toprogram the capacitor of FIG. 3g to a particular desired value, theparticular combination of capacitor array elements C1 . . . Cn to beincorporated into the final capacitor structure is first ascertained.For example, the desired capacitance value may be compared against apredefined table which lists the possible combinations of incorporatedcapacitor array elements and the capacitance values that result thereby.

To select a given capacitor array element for incorporation into thefinal capacitor array structure, a contact mask is employed to perform acontact etch. If a capacitor array element site is provided with acontact hole (through intermediate oxide layer 42) to facilitateelectrical contact with a subsequently deposited conductive layer, thatcapacitor array element is selected for incorporation. On the otherhand, if a capacitor array element is not provided with a contact holethrough the intermediate oxide layer 42 that overlies it, no electricalcontact may be formed between that capacitor array element and thesubsequently deposited conductive layer. Consequently, the lattercapacitor array element may be through of as being non-selected, i.e.,makes no contribution (except for its parasitic capacitance) to thecapacitance value of the final capacitor structure.

As shown in FIG. 3h, a contact hole 44 is created by etching through theintermediate oxide 42 to expose polysilicon top plate 40b. FIG. 3i showsthe deposition of a metal layer 46, which makes contact with polysilicontop plate 40b through contact hole 44. This metal layer acts as acontinuous top plate connected to all selected capacitor array elements,advantageously minimizing the parasitic effects of resistance andinductance.

As can be seen in FIG. 3h, the capacitor array element associated withpolysilicon top plate 40(b) is selected for incorporation into the finalcapacitor structure. In contrast, no contact hole is made withpolysilicon top plate 40a, and the capacitor array element associatedtherewith is left decoupled from the final capacitor structure. However,there exists a parasitic capacitor consisting of two capacitors inseries. The first capacitor is formed with the metal acting as the topplate, the intermediate oxide acting as the primary dielectric, and thepolysilicon layer acting as the bottom plate. The second capacitor isformed with the polysilicon layer acting as the top plate, the gateoxide acting as the dielectric, and the n⁺layer acting as the bottomplate. This parasitic capacitor, which is associated with the site ofthe non-selected capacitor array member, still contributes to thecapacitance value of the final capacitor structure in the mannerdiscussed in connection with FIG. 1c. In practice, the parasiticcapacitance value is much smaller than the capacitance value of thenormal capacitor array element typically one twentieth to one fortiethof the non-selected capacitor array member. Following the metaldeposition step of FIG. 3i a passivation layer 50 is deposited in aconventional manner to protect the entire structure, as shown in FIG.3j.

It should be emphasized that in the above discussed embodiment, theseparate capacitor array elements are always present. Whether a givencapacitor array element is selected for incorporation or left out of thefinal capacitor structure depends on whether a contact hole is providedin the intermediate oxide layer above that capacitor array element tocreate an electrical path to its top plate. Thus, the value of thecapacitor structure that results is determined by appropriatelyprogramming the presence or absence of selected contact holes on thecontact mask.

While this invention has been described in terms of several preferredembodiments, there are alterations, permutations, and equivalents whichfall within the scope of this invention. By way of example, although theinventive concept has been discussed, for east of illustration, withreference to n+type substrates, n type or p type materials could bereversed in a given process implementation. Further, the presentinventive concepts also apply equally well to capacitor arrays employingdifferent types of dielectric materials, doping concentrations, as wellas those not having an epitaxial layer. Additionally, although theprogrammability feature is facilitated through the use of a contact maskin this discussion, it should be borne in mind that a programmablepassive device may be facilitated through the use of the metal mask, thevia mask between metal 1 and metal 2 layers, poly mask, active mask, andthe like. As a further example, the inventive concepts discussed hereinare also applicable to passive devices (such as capacitors, resistors,inductors, and the like) which are integrated with active components(such as transistors, diodes, and the like) on the same integratedcircuit. It should also be noted that there are many other alternativeways of implementing the methods and apparatuses of the presentinvention. It is therefore intended that the specification herein beinterpreted as including all such alterations, permutations, andequivalents as fall within the true spirit and scope of the presentinvention.

What is claimed is:
 1. A method for endowing an integrated passivedevice array structure with a programmable value during manufacturing,comprising: forming a substantially conductive first layer; forming aplurality of integrated passive device array elements of said integratedpassive device array structure above said substantially conductive firstlayer, wherein some of the integrated passive array elements have afirst value and others have a second value wherein the first value andthe second value are different; forming an insulating layer above saidplurality of passive device array elements; and; selectively formingvias in said insulating layer, said vias facilitating electricconnection between selected ones of said plurality of passive devicearray elements with a substantially conductive second layer subsequentlydeposited above said insulating layer, thereby programming apre-selected value into the integrated passive device array structure.2. The method of claim 1 wherein said plurality of passive device arrayelements represent capacitors.
 3. The method of claim 2 wherein saidcapacitors have dielectric portions formed in an oxide layer, said oxidelayer being disposed between said substantially conductive first layerand said insulating layer.
 4. The method of claim 3 wherein areas ofsaid dielectric portions are selected to permit values of said pluralityof said passive device array elements to relate to one another in abinary manner.
 5. The method of claim 1 wherein said selectivelyformning vias including selecting an appropriate mask to etch throughsaid insulating layer.
 6. A method for forming an integrated passivedevice array structure having a programmable value, comprising: forminga substantially conductive first layer; electrically coupling saidsubstantially conductive first layer with a plurality of passive devicearray elements of said integrated passive device array structure, saidplurality of passive device array elements being disposed above saidsubstantially conductive first layer; and electrically coupling selectedones of said plurality of passive device array elements with asubstantially conductive second layer formed above said passive devicearray element to form said integrated passive device array structure,said selected ones of said plurality of passive device array elementsrepresenting a subset of said plurality of passive device arrayelements, thereby programming a value into the integrated passive devicearray structure.
 7. The method of claim 6 wherein a value of saidintegrated passive device array structure is substantially determined byan aggregate of values of said selected ones of said plurality ofpassive device array elements.
 8. The method of claim 6 wherein saidselected ones of said plurality of passive device array elements areconfigured to be electrically coupled in parallel between saidsubstantially conductive first layer and said substantially conductivesecond layer.
 9. The method of claim 6 further comprising forming saidplurality of passive device array elements above said substantiallyconductive first layer, including forming individual ones of saidplurality of passive device array elements, values of said individualones of said plurality of passive device array elements being related ina binary manner.
 10. The method of claim 6 further comprising formingsaid plurality of passive device array elements above said substantiallyconductive first layer, including forming individual ones of saidplurality of passive device array elements in an oxide layer, said oxidelayer being disposed between said substantially conductive first layerand said substantially conductive second layer.
 11. The method of claim10 further comprising: forming an insulating layer above said oxidelayer; and furnishing each of said selected ones of said plurality ofpassive device array elements with a via through said insulating layerto permit said substantially conductive second layer to electricallycouple with said each of said selected ones of said plurality of passivedevice array elements.
 12. The method of claim 11 wherein at least oneof said plurality of passive device elements is selected to beelectrically decoupled from said substantially conductive second layer.13. The method of claim 11 wherein said plurality of passive devicearray elements represent capacitors.
 14. A method of forming aprogrammed integrated capacitor during manufacturing, the methodcomprising: forming a substantially conductive first layer; forming aplurality of integrated capacitor elements to create an integratedcapacitor array structure, each of the integrated capacitor elementsbeing electrically connected to the substantially conductive firstlayer; forming an insulating layer that electrically isolates theplurality of integrated capacitor elements; forming a substantiallyconductive second layer; electrically coupling a selected number of theintegrated capacitor elements to the substantially conductive to programa capacitance value into the integrated capacitor array structure.